02 Mar 2021

SDP on Digital System Design using VHDL


Event Title: SDP on Digital System Design using VHDL
Event category  5 days Student Development Program under TEQIP
About Event


Department of Electronics & Communication Engineering is organizing a 5 days online Short Term Training Program on “VHDL Verilog” for ECE, CSE & EEE students. The resource person is from a reputed company Insergo Technologies, Dehradun. This program is to make students aware about the latest trends and technology used in the field of digital design language.
AIM of the Events


Hardware design of digital circuits using Verlog VHDL with the help of combinational and sequential circuits
Content of the Event    Theoretical and Practical exposure on Hardware design using VHDL languages
Highlights of Events


Hardware design using hardware descriptuion languages , sequential and combinational circuit design techniques and control circuit design.
Speakers of the Events:


NAME Mr. Rahul Panwar, Technical Head
Department Name Electronics and Communication Engineering
 Course Name B.Tech(ECE, EEE)
Date Time & Venue of Events: 02nd – 6th March, 2021 | Offline Mode (I) 10:00 AM to 12:00AM

(II) 02:00PM to 04:00PM

Event Coordinator &Organizing Team Members Mr. Gautam Shah , Assistant Professor ECE
Contact Person Mr. Mukesh Pathela (8979690062), HOD ECE

Workshop Registration Form




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